Many electronic products such as a personal computer, digital camera and cellular telephone employ a fair amount of memory to store significant amounts of information. Different storage media in conjunction with varying storage techniques are employed to manage the information associated with a particular application. Several examples of memory devices include a hard drive, compact disc, flash memory, static random access memory (SRAM) and dynamic random access memory (also referred to as a DRAM).
Each memory device has a unique set of advantages and disadvantages that form a basis to employ the device in a particular application. For instance, some memory devices such as a hard drive and flash memory store information without a need for an uninterruptible power supply. Some other memory devices such as a compact disc allow for a swapping of a data carrier thereby providing an environment for mass storage. Some other memory devices such as a SRAM allow for very fast access to random data thereby providing a solution for an application wherein latency is a concern.
An advantage associated with a DRAM is that the memory device is significantly less expensive than other memory devices such as a flash memory or SRAM. The DRAM, however, suffers from a number of drawbacks. For instance, the DRAM calls for a continuous power source to operate, and the DRAM is slower than some memory devices such as the SRAM. The DRAM also performs internal refresh cycles to maintain the information stored in the memory cells thereof. A refresh current associated with the internal refresh cycles contributes to a standby current of the DRAM. Consequently, a value of the standby current for the DRAM is typically much larger in comparison to other memory devices. Also, the internal refresh cycles block the DRAM from being accessed, making it more difficult to attain a certain data throughput and providing a lower system latency. Finally, additional logic is often employed in a DRAM control system to manage the internal refresh cycles.
Although the aforementioned restrictions are prevalent, the DRAM technology has not only survived, but it has been developed into specialized categories aimed at populating areas of the memory market that were previously occupied by other memory devices such as the flash memory or SRAM. As an example, while a reduced latency DRAM employs a larger surface area, the memory device was developed to compete with the SRAM for applications demanding faster access times such as network routers. Also, low power DRAMs were developed for hand held applications such as a cellular telephone wherein an extended battery life is a major advantage.
New applications for handheld devices such as a cellular telephone is causing the memory demands associated therewith to increase significantly. At the same time, there is a fierce battle to control product costs to access a broader customer base. The DRAMs could be a viable contender to fill this void if the standby current is reduced.
Regarding the architecture, the DRAMs store information on capacitors (i.e., the memory cells) that are connected to sense amplifiers using an access transistor. A two dimensional array structure is used for the memory cells and their corresponding transistors. A row of transistors is selected by a common word-line connected to the gates of the transistors. While the source of the transistor is connected to the memory cell, the drain is connected to a bit-line which is connected to the sense amplifier. While a plurality of transistors is connected to each bit-line, typically a single transistor is active at a time (i.e., typically only one word-line is active). This configuration allows one row of the memory array to be read out, be amplified and then be written back into the corresponding memory cells at a time.
Since a capacitance of a memory cell is typically less than a capacitance of the bit-line (e.g., around 5 times), the sense amplifier should be able to sense small differences in the bit-line voltage. A technique that is commonly used pre-charges the bit-line to an intermediate voltage level that is between an upper and lower level stored in the memory cells. The negative plate of the capacitor is connected to the intermediate voltage (or an equal voltage on a separate net) as well.
The sense amplifier is typically a differential amplifier that is connected to two independent bit-lines. When a row is activated, one of the bit-lines is connected to an actual memory cell. As a result, the bit-line that is connected to a memory cell exhibits either a slight increase in voltage level (when a high voltage level is stored in the memory cell) or a slight decrease in voltage level (when a low voltage level is stored in the memory cell), while the other bit-line remains at the intermediate voltage level. The difference between the voltage levels of the bit-lines is then detected by the sense amplifier.
Since DRAM memory cells are capacitors, the memory cells lose the information stored therein over time. The memory cells, therefore, are refreshed (read out and rewritten) during a defined period of time. The period of time is typically designated in a product specification as refresh or retention time and is often in the range of 64 to 256 milliseconds (ms). The period of time that a memory cell can maintain its data depends on a wide range of design and technology parameters.
Regarding memory fails, apart from shorts resulting from process inaccuracies (e.g., foreign materials, mask errors) that cause hard fails, other types of fails such as retention fails and bulk fails may be distinguished. The retention fails are defined as fails resulting from weak memory cells or memory cells that exhibit some type of marginality. The retention fails may be reproduced and often repaired. Bulk fails occur due to a normal statistical discharge of memory cells and are random in nature. FIG. 1 demonstrates a typical relationship of memory cell fails versus the time between refreshes or a refresh time of a DRAM.
During a production test, the DRAMs are tested for fails and are subsequently repaired using redundant array elements that are available on an integrated circuit employing the DRAMs. The tests are normally performed with a retention time that is several times larger than a retention time of the DRAM under test (e.g., 256 ms test for a 64 ms component). Inasmuch as the retention fails are predictable, theoretically it is possible to repair the DRAMs at a refresh time close to the border when the bulk fails start to appear. In reality, however, this is not plausible because the number of retention fails at the point of the bulk fails is too large to be completely repaired by redundancy. Therefore, the production tests are usually performed employing a retention time that is several times smaller than the time when a first bulk fail appears. Nevertheless, the number of retention fails is relatively small in comparison to the total number of memory cells that form the DRAMs of the integrated circuit.
The refresh time is inversely proportional to a standby current of the memory device. Even when inactive, the DRAM executes refresh cycles internally so as to avoid a loss of information. The longer a period between refreshes, the lower the standby current. For DRAMs employable in mobile applications (e.g., cellular telephone), the standby current can have a significant impact on a battery life thereof.
Accordingly, what is needed in the art is system and method for use with a DRAM that reduces the effects of the refresh cycles on the standby current of the DRAM without substantially hindering an operation thereof in view of the escalating memory demands of an electronic device employing the DRAM to advantage.